The present invention relates to a switched capacitor device for use in an electronic filter, voice recognition circuit or voice synthesizing circuit.
FIGS. 1A and 1B are circuit diagrams showing the basic circuit configuration of a switched capacitor circuit, while FIG. 2 shows an equivalent circuit thereof. In the circuit shown in FIGS. 1A and 1B, a first stationary contact "a" of a switch S is connected to an input terminal 11, and a second stationary contact "b" is connected to an output terminal 12. A common contact "c" is grounded through a switched capacitor Cs. The input and output terminals 11 and 12 are kept at potentials corresponding to input and output voltage signals Vi and Vo, respectively, with reference to ground. Referring to FIG. 1A, when the switch S is connected to the side of the contact "a" to be connected to the input terminal 11, charge Q1 charged on the capacitor Cs is given by Q1=Cs.multidot.Vi. On the other hand, when the switch S is connected to the side of the contact "b" to be connected to the output terminal 12 as in FIG. 1B, charge Q2 stored on the capacitor Cs is given by Q2=Cs.multidot.Vo. This means that charge .DELTA.Q (total amount of charge transfer) is transferred from the input terminal 11 to the output terminal 12 when the switch S is switched from the input terminal 11 to the output terminal 12. Charge .DELTA.Q is given by: EQU .DELTA.Q=Q1-Q2=Cs(Vi-Vo) (1)
If the switch S is switched at a switching frequency (per second) of fs, an average current i flowing from the input terminal 11 to the output terminal 12 is given by: EQU I=.DELTA.Q.multidot.fs=Cs(Vi-Vo)fs (2)
If the switching frequency fs of the switch S is sufficiently greater than the frequencies of the voltages Vi and Vo, the average current i becomes equal to a current which is determined by the instantaneous values of the voltages Vi and Vo. Therefore, the circuit shown in FIGS. 1A and 1B becomes equivalent to a circuit shown in FIG. 2 wherein an equivalent resistor R is connected between the input terminal 11 and the output terminal 12 where R is given by: EQU R=(Vi-Vo)/i=1/(Cs.multidot.fs) (3)
A switched capacitor circuit is thus provided wherein one end of a switched capacitor Cs whose other end is connected to a reference potential (ground) is switched between two different potentials such that an equivalent resistor R is connected between these two different potentials.
FIG. 3 shows a circuit diagram of a mirror integrator having an operational amplifier 31. The input-output characteristic of the integrator is given by: EQU Vo/Vi=1/(S.multidot.Rs.multidot.Cf) (4)
where
Vi is the input voltage signal;
Vo is the output voltage signal;
Rs is the resistance of an input resistor connected between the input terminal 11 and the inverting input terminal (-) of the operational amplifier 31;
Cf is the capacitance of a feedback capacitor connected between the output terminal of the operational amplifier 31 and the inverting input terminal (-) thereof; and
S is the Laplacian.
Referring to FIG. 3, reference symbols VDD and VSS denote power sources, and the non-inverting input terminal (+) of the operational amplifier 31 is grounded.
FIG. 4 is a circuit diagram of a mirror integrator which has a switched capacitor circuit 41 in place of the input resistor Rs in the circuit shown in FIG. 3. The input-output characteristic of the mirror integrator is yielded by substitution of R in equation (3) with Rs in equation (4) as follows: EQU Vo/Vi=fs/{S(Cf/Cs)} (5)
It is seen from equation (5) above that the input-output characteristic of the mirror integrator shown in FIG. 4 is determined by a function, more specifically, a linear function of the capacitance ratio of the capacitors Cs and Cf and the switching frequency fs of the switch S. This means that an integration constant can be varied in proportion to the switching frequency fs. Therefore, a filter including the mirror integrator shown in FIG. 4 can switch the filtering frequency in proportion to the switching frequency fs.
FIGS. 5A and 5B, and 6A and 6B respectively show mirror integrators equivalent to the mirror integrator shown in FIG. 4. In the mirror integrators shown in FIGS. 5A and 5B, and 6A and 6B, switched capacitor circuits 50 and 51 respectively have two switches S1 and S2 which switch both ends of the capacitor Cs simultaneously. A first stationary contact "a1" of the switch S1 is connected to the input terminal 11, a second stationary contact "b1" is grounded, and the common contact is connected to one end of the capacitor Cs. A first stationary contact "a2" of the switch S2 is connected to the inverting input terminal (-) of the operational amplifier 31, a second stationary contact "b2" is grounded, and the common contact is connected to the other end of the capacitor Cs.
In the mirror integrator shown in FIGS. 5A and 5B, the switched capacitor circuit is used as a resistor having a positive resistance.
When the switches S1 and S2 are connected to the sides of the second stationary contacts "b1" and "b2" as shown in FIG. 5A, charge on the capacitor Cs is discharged and is therefore zero. When the switches S1 and S2 are switched to the sides of the first stationary contacts "a1" and "a2", charge Q expressed by equation (6) below is charged on the capacitor Cs: EQU Q=Cs (Vi-Vi') (6)
where Vi is the input voltage signal supplied to the input terminal 11; and
Vi' is an input voltage signal supplied to the inverting input terminal (-) of the operational amplifier 31.
The average current i to flow through the capacitor Cs at this time is given by: EQU i=Cs(Vi-Vi )fs (7)
where fs is the switching frequency of the switches S1 and S2.
The resistance of the equivalent resistor R between the stationary contacts "a1" and "a2" is given by: EQU R=(Vi-Vi')/i=1/(Cs.multidot.fs) (8)
Equation (8) is the same as equation (3). It is seen from this that the switched capacitor circuit 50 shown in FIGS. 5A and 5B is equivalent to the switched capacitor circuit 41 shown in FIG. 4.
In the mirror circuit shown in FIGS. 6A and 6B, the switched capacitor circuit 51 is used as a resistor having a negative resistance.
When the switches S1 and S2 are switched to the sides of the first stationary contact "a1" and the second stationary contact "b2", respectively, as shown in FIG. 6A, charge Q as expressed by equation (9) below is stored on the capacitor Cs: EQU Q=Cs.multidot.Vi (9)
When the switches S1 and S2 are switched to the sides of the second stationary contact "b1" and the first stationary contact "a2", respectively, as shown in FIG. 6B, charge Q expressed by equation (9) above stored on the capacitor Cs is supplied to the inverting input terminal (-) of the operational amplifier 31. Therefore, if the switching frequency fs of the switches S1 and S2 is sufficiently higher than those of the voltages Vi and Vi', an equivalent resistance circuit expressed by R=1/(Cs.multidot.fs) is provided.
A conventional switched capacitor integrator to be used as a mirror integrator as in FIGS. 4, 5A and 5B, and 6A and 6B requires one power source terminal connected to reference potential Vref in addition to two power source terminals connected to two power sources VDD and VSS. Therefore, if such a switched capacitor integrator is included in a single device together with a general RANDOM LOGIC using two power sources (VDD and VSS), a reference power source terminal is required in addition to two power source terminals.
However, an increase in the number of the power source terminals presents a big problem especially in integrated circuits. More specifically, since the circuit configuration becomes complex, the time interval required for circuit design is prolonged, the chip area is increased, and the pattern design becomes complex to allow connection of three power source terminals. This also makes the design of the printed substrate complex and raises the manufacturing cost of the circuit.
FIG. 7 shows a circuit diagram of a band pass filter comprising a switched capacitor integrator as described above having switched capacitor circuits. An input voltage signal Vi supplied to an input terminal 71 is supplied to the inverting input terminal (-) of a first operational amplifier 31.sub.1 through an input capacitor Cs11. Power source voltages from the power sources VDD and VSS are applied to the first operational amplifier 31.sub.1. The output terminal of the first operational amplifier 31.sub.1 is connected to a switched capacitor circuit 72 of the next stage as well as to the inverting input terminal (-) thereof through a feedback capacitor Cf1. The non-inverting input terminal (+) of the first operational amplifier 31.sub.1 is connected to the reference potential Vref or ground. An output voltage signal Va from the first operational amplifier 31.sub.1 is supplied to the inverting input terminal (-) of a second operational amplifier 31.sub.2 through the switched capacitor circuit 72 serving equivalently as a positive resistor. Power sources VDD and VSS are connected to the second operational amplifier 31.sub.2. The output terminal of the second operational amplifier 31.sub.2 is connected to an output terminal 73 of the device as well as to the inverting input terminal (-) thereof through a feedback capacitor Cf2. The non-inverting input terminal (+) of the second operational amplifier 32.sub.2 is connected to the reference potential Vref or ground. The output terminal of the second operational amplifier 32.sub.2 is connected to the inverting input terminal (-) thereof through a switched capacitor circuit 74 serving equivalently as a positive resistor, as well as to the inverting input terminal (-) of the first operational amplifier 31.sub.1 through a switched capacitor circuit 75 serving equivalently as a negative resistor, so that the output signal from the second operational amplifier may be fed back to the inputs of the first and second operational amplifiers 31.sub.1 and 31.sub.2.
The mode of operation of the band pass filter of this configuration will now be described.
The input voltage signal Vi supplied to the input terminal 71 is amplified by the first operational amplifier 31.sub.1 in accordance with the capacitance ratio of the input capacitor Cs11 and a feedback capacitor Cf1. The first operational amplifier 31.sub.1, the feedback capacitor Cf1 and the switched capacitor circuit 75 together function as an integrator having an integration constant which is determined by the capacitances of the capacitors Cs12 and Cfl and the switching frequency fs of the switches Sl and S2 of the switched capacitor circuit 75. The output voltage signal Va from the first operational amplifier 31.sub.1 is the sum of the amplified value of the input voltage signal Vi and the integrated value of the output voltage signal Vo. Since the switched capacitor circuit 75 with the switched capacitor Cs12 serves as a negative resistor, the integrated value of the integrated value of the output voltage signal Vo has a negative sign. The output voltage signal Va from the first operational amplifier 31.sub.1 becomes an input signal to the integrator consisting of the switched capacitor circuit 72, the second operational amplifier 31.sub.2, and the feedback capacitor Cf2. This integrator operates such that the output voltage signal Vo from the second operational amplifier 31.sub.2 is fed back by the switched capacitor circuit 74 and the feedback capacitor Cf2.
Thus, the output voltage signals Va and Vo from the first and second operational amplifiers 31.sub.1 and 31.sub.2 are given by: EQU Va=(Cs11/Cf1)Vi+{Cs12/(S.multidot.Cf1)}fs.multidot.Vo (10) EQU Vo=-(Cs21/S.multidot.Cf2)fs.multidot.Va-(Cs22/S.multidot.Cf2)fs.multidot.Vo (11)
Substitution of equation (10) in equation (11) gives a transfer function H(s) expressed as follows: ##EQU1##
It is well known that the characteristic relation of the band pass filter having the transfer function H(s) which is a quadratic function may be given as follows: EQU H(s)=(G.multidot..omega.C.multidot.S)/{S.sup.2 +(.omega.C/Q)S+.omega.C.sup.2 } (13)
where .omega.C is the center frequency of the band pass filter, Q is the characteristic constant, G is the filter gain, and S is the Laplacian.
If G=1, we obtain: EQU Cs11/Cf1=1 (14) EQU (Cs21/Cf2)fs=(Cs12/Cf1)fs=.omega.C (15) EQU (Cs22/Cf2)fs=.omega.C/Q (16)
Therefore, a desired band pass filter may be obtained by suitably determining the respective elements expressed by equations (14), (15) and (16).
The conventional band pass filter of this type requires a power source terminal which is connected to the reference potential Vref or ground in addition to the two power source terminals which are connected to the power sources VDD and VSS for amplification. Therefore, a device including a band pass filter and a general RANDOM LOGIC using the two power sources VDD and VSS requires a reference power source terminal in addition to the two power source terminals.
However, as has been described above with reference to a conventional mirror integrator, this leads to complexity in the circuit configuration, an increase in the chip area, and complexity of pattern design due to the presence of the three power source terminals. Accordingly, the design of a printed substrate for mounting an integrated circuit becomes complex, and the manufacturing cost of the circuit is high.